? semiconductor components industries, llc, 2011 august, 2011 ? rev. 6 1 publication order number: NTD5802N/d NTD5802N, nvd5802n power mosfet 40 v, single n ? channel, 101 a dpak features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? msl 1/260 c ? aec q101 qualified ? 100% avalanche tested ? aec q101 qualified ? nvd5802n ? these devices are pb ? free and are rohs compliant applications ? cpu power delivery ? dc ? dc converters ? motor driver maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent (r jc ) (note 1) steady state t c = 25 c i d 101 a t c = 85 c 78 power dissipation (r jc ) (note 1) t c = 25 c p d 93.75 w continuous drain cur- rent (r ja ) (note 1) t a = 25 c i d 16.4 a t a = 85 c 12.7 power dissipation (r ja ) (note 1) t a = 25 c p d 2.5 w pulsed drain current t p =10 s t a = 25 c i dm 300 a current limited by package t a = 25 c i dmaxpkg 45 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 50 a drain to source dv/dt dv/dt 6.0 v/ns single pulse drain ? to ? source avalanche en- ergy (v dd = 32 v, v gs = 10 v, l = 0.3 mh, i l(pk) = 40 a, r g = 25 ) e as 240 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. case 369c dpak (bent lead) style 2 marking diagrams & pin assignment 40 v 4.4 m @ 10 v r ds(on) 101 a i d v (br)dss 7.8 m @ 5.0 v http://onsemi.com 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on p age 6 of this data sheet. ordering information n ? channel d s g 1 gate 2 drain 3 source 4 drain yww 58 02ng y = year ww = work week 5802n = device code g = pb ? free package 50 a
NTD5802N, nvd5802n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 1.6 c/w junction ? to ? ambient ? steady state (note 1) r ja 60 junction ? to ? ambient ? steady state (note 2) r ja 105 1. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 10 a 40 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 40 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 1.0 a t j = 150 c 50 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 3.5 v negative threshold temperature coefficient v gs(th) /t j ? 7.4 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 50 a 3.6 4.4 m v gs = 5.0 v, i d = 50 a 6.5 7.8 forward transconductance gfs v ds = 15 v, i d = 15 a 16.8 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 12 v 5300 pf output capacitance c oss 850 reverse transfer capacitance c rss 550 input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 5025 pf output capacitance c oss 580 reverse transfer capacitance c rss 400 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 50 a 75 100 nc threshold gate charge q g(th) 6.0 gate ? to ? source charge q gs 18 gate ? to ? drain charge q gd 15 switching characteristics (note 4) turn ? on delay time t d(on) v gs = 10 v, v ds = 20 v, i d = 50 a, r g = 2.0 14 ns rise time t r 52 turn ? off delay time t d(off) 39 fall time t f 8.5 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NTD5802N, nvd5802n http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 50 a t j = 25 c 0.9 1.2 v v gs = 0 v, i s = 20 a t j = 25 c 0.8 1.0 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 50 a 25 ns charge time ta 15 discharge time tb 10 reverse recovery charge q rr 15 nc
NTD5802N, nvd5802n http://onsemi.com 4 typical performance characteristics 7 v 100 1000 10000 100000 2 6 10 14 18 22 26 30 34 38 v gs , gate ? to ? source voltage (v) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (a) figure 3. on ? resistance vs. drain current figure 4. on ? resistance vs. drain current and gate voltage i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 0 50 100 150 200 23456 v ds 10 v t j = 25 c t j = ? 55 c t j = 100 c 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 30 50 70 90 110 130 150 170 190 v gs = 5 v t j = 25 c v gs = 10 v 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ? 50 ? 25 0 25 50 75 100 125 150 175 i d = 50 a v gs = 10 v v gs = 0 v t j = 150 c t j = 100 c 0 20 100 140 200 012 56 v ds , drain ? to ? source voltage (v) i d , drain current (a) 34 40 60 80 120 160 180 t j = 25 c v gs = 5 v 10 v 6 v 4 v 4.5 v 4.2 v 3.8 v 3.6 v r ds(on) , drain ? to ? source resistance ( ) i d , drain current (a) t j = 150 c t j = ? 55 c v gs = 10 v 0.002 0.006 0.010 10 30 70 150 190 90 130 0.004 0.008 t j = 25 c 50 110 170
NTD5802N, nvd5802n http://onsemi.com 5 typical performance characteristics v sd , source ? to ? drain voltage (v) 1 10 100 1000 1 10 100 figure 7. capacitance variation q g , total gate charge (nc) figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v gs , gate ? to ? source voltage (v) figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) figure 10. diode forward voltage vs. current t, time (ns) i d = 50 a t j = 25 c v gs q ds v dd = 20 v i d = 50 a v gs = 10 v t r t d(off) t d(on) t f q gs q t v ds v ds , drain ? to ? source voltage (v) gate ? to ? source or drain ? to ? source voltage (v) c, capacitance (pf) 0 1000 2000 3000 4000 5000 6000 7000 8000 105 0 5 10152025303540 c iss c oss c rss v gs = 0 v t j = 25 c v ds v gs 0 3 6 9 12 15 020406080 0 6 12 18 24 30 v gs = 0 v t j = 25 c 0.4 0.8 1.4 0.6 1.0 1.2 0 10 20 30 40 50 60 i s , source current (a) figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) i d , drain current (a) 0.1 10 100 1000 0.1 10 100 10 s 100 s 1 ms 10 ms dc v gs = 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 1 1
NTD5802N, nvd5802n http://onsemi.com 6 typical performance characteristics 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 t, pulse time (s) figure 12. thermal response r(t), effective transient thermal resistance ( c/w) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse ordering information order number package shipping ? NTD5802Nt4g dpak (pb ? free) 2500 / tape & reel nvd5802nt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NTD5802N, nvd5802n http://onsemi.com 7 package dimensions dpak case 369c ? 01 issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NTD5802N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
